In the production of integrated circuits, the yield of dies from wafers may have a significant impact on the performance of a manufacturer. Accordingly, any steps taken during the manufacturing of integrated circuits which improve wafer yield or reduce the time and resources for determining functioning dies is important. Wafer testing is performed before a wafer is sent to die assembly during semiconductor device fabrication. Individual integrated circuits on the wafer are tested for functional defects by applying special test patterns to them. The wafer testing is performed using a piece of test equipment called a wafer probe tester in a process referred to as a probe test or wafer sorting process. Nearly all integrated circuit wafers are probed for some basic performance verification. Because variations in materials and the fabrication process result in a range of performance, all dies are not identical, even on the same wafer. While dies on wafers generally receive at least a set of key DC measurements, a full set of tests over the full range of operating frequencies and input/output conditions may be specified, verifying the performance of each die that will be packaged or become part of an integrated subsystem. Various measurements allow the better dies to be separated from the normal or below normal performing dies. An accurate and repeatable test system can sort the individual die into performance categories in a process generally referred to as binning. That is, a die is assigned a bin number based upon the results of a series of tests, where the bin number provides an indication of the performance of the die. For example, a die that passes a greater number of tests would be placed in a different bin indicative of different operating characteristics, such as operating frequency. Individual die that fail testing are marked with an ink dot, or indicated on a wafer map, so they are scrapped when the wafer is diced to avoid the cost of packaging known bad dies. A lot of wafers is generally tested together, before being shipped to another location where dies which have not failed are packaged as integrated circuit packages.
Two primary issues in the testing of wafers are the performance of the wafer sorter probe card itself, and calibration of the test system. Because integrated circuit testing is a sensitive mechanical process, issues related to the performance of the wafer sort probe card include the reliable contact of the probe site to the wafer test points, and the accurate positioning of the probes. Wafer sort probe cards are prone to mis-binning due to usage or physical damage. Information related to sort bin and probe card site number information is saved in a text file to be processed at a later time. The sorted wafer is then taken off the wafer sorter and may be shipped to the assembly site as a part of a lot which has been tested. According to conventional methods, the bin and site information is summarized at some later time. Bin totals by probe site number and the difference in bin statistics between probe card site numbers are calculated. The summaries of the site and composite wafer maps do not occur while the wafers of a lot are on the wafer sorter, and may even occur after the wafer has been shipped to assembly. Accordingly, the verification of the mis-binning requires that the wafer be setup for wafer sort again and retested. This verification according to conventional methods wastes tester time and other resources such as the additional time to relocate and return the lot of wafers to the wafer sorter and the time required by the test operator.
Accordingly, there is a need for an improved method of and system for monitoring the functionality of a wafer probe site.